Background Art
As is well known, processes for manufacturing integrated electronic structures which include non-volatile memory cells, that is matrices of cells organized into rows and columns, using a dual level of polysilicon with an interpoly dielectric isolation layer interposed between the two polysilicon levels, are extensively used in the industry. These processes provide for a first masking and implanting step to define well regions in a semiconductor substrate. The well regions have a different type of conductivity from that of the substrate.
Conventional processes provide for the initial definition of the active areas of the various integrated devices (transistors, memory cells, etc.). Usually, a subsequent oxide growing step also is provided to form field isolation regions formed by a thick oxide layer which isolates the discrete active areas from each other. In some cases, the process may include a relatively heavy implantation for threshold raising purposes, which is usually performed in the matrix area, that is in the region where the memory cells are formed. However, this operation alternatively may be carried out at a later stage of the manufacturing process.
To enable all the aspects of the present invention to be more clearly understood, it is useful to summarize the sequence of process steps which result, at the present state of the art, in the formation of an integrated circuit of non-volatile memory cells.
A thin oxide layer, called the gate oxide, is grown over the active areas. A first layer of polysilicon, referred to as the first-level polysilicon or Poly1, then is deposited onto the gate oxide. Thereafter, a masking and etching step usually is carried out for a preliminary definition of the Poly1 which is to form part of the floating gate regions of the memory cells. An intermediate isolation dielectric layer, called the interpoly, next is grown and/or deposited over the entire resultant structure. This dielectric layer may be a stack structure, i.e. comprised of a first oxidation layer overlaid by a thin layer of nitride, and a third layer of nitride oxidation. Such a dielectric layer is referred to as the ONO layer.
At this stage of the manufacturing process, a masking step is carried out to thoroughly remove the interpoly layer, except from the matrix area occupied by the memory cells. For this reason, the mask employed here is commonly termed the "matrix" mask. Subsequently, a second layer of polysilicon, known as the second-level polysilicon or Poly2, is deposited and doped. Inside the matrix area, the Poly2 will remain isolated from the Poly 1 by the interpoly layer. In the regions outside the area occupied by the cell matrix, i.e. the regions accommodating the transistors and other external circuitry devices, the Poly2 layer overlies the existing Poly1 layer directly.
The above process steps are described in U.S. Pat. No. 4,719,184 issued to the Assignee of Applicants.
As previously mentioned, a further masking step may become necessary in some cases to provide a slight implant for adjusting the light voltage shift ("LVS") threshold of certain transistors in the external circuitry. Other low-threshold transistors, or so-called native transistors, must instead be screened off this implant. Yet another masking step, and associated etching, allows the channel length of the transistors in the circuitry to be defined. A mask, designated Poly2, is used during this step which also allows the second-level polysilicon to be defined in the matrix area, with the etching stopped short of the intermediate interpoly layer.
An improvement in the above manufacturing method has been aimed at the formation of the native transistors. This improvement is described in European Patent Application No. 96830021.0 by the Applicant. In essence, a much more effective way of forming native transistors, within a standard manufacturing process like that just described, has been provided. This method substantially eliminates the masking step for threshold adjustment in the external circuitry transistors, thereby lowering the manufacturing costs. The same matrix mask that is used for etching away the interpoly dielectric layer is used to define the channel length of the native transistors located outside the area occupied by the matrix. Accordingly, instead of carrying out the LVS step, the matrix mask is suitably modified and also employed for masking the channel area within the active area of the native transistors located outside the matrix area. These native transistors are formed unconventionally with respect to the other raised-threshold transistors. The aforementioned European Patent Application discloses all the details about this formation.
The present invention fits in the same line of research that resulted in the method just described. The underlying technical problem of this invention is to provide a novel method of manufacturing a P-channel native MOS transistor, within the frame of a process for manufacturing non-volatile memories, which method has features appropriate to ensure the desired formation regardless of the threshold adjusting implantations applied to other enhancement transistors in the external circuitry of the matrix area, and therefore to avoid one masking level. In other words, the aim is to enable a P-channel native transistor to be made without one masking level, while preventing subsequent LDD implantations from altering the threshold of the transistor.